IEEE Senior Member
Esteban Garzón, Ph.D.
Assistant Professor · VLSI Design Engineer
Department of Computer Engineering, Modeling, Electronics and Systems (DIMES), University of Calabria, Italy
I design domain-specific hardware accelerators and emerging memory technologies — from STT-MRAM and content-addressable memory to in-memory computing architectures — for energy-efficient, data-intensive applications.
- 73 Publications
- 47 Journal Articles
- 25 Conference Papers
- 3 Silicon Tapeouts
- 15 Awards & Honours
Welcome
I am an Assistant Professor (RTD-A; non-tenured track) at the University of Calabria. My research interests include domain-specific hardware accelerators, electronics/spintronics, and standard and emerging technologies for logic & memory, and low-power applications.
I received my Ph.D. degree (Hons.) in Electronics Engineering from the University of Calabria in 2022, under the supervision of Prof. Marco Lanuzza and Prof. Adam Teman. In July 2024, I received the National Scientific Habilitation (ASN) for Associate Professor of Electronics (Sector 09/E3) in Italian Universities.
In 2019–2020 I was a visiting Ph.D. student at Emerging Nanoscaled Circuits and Systems (EnICS) laboratories, Bar-Ilan University, Israel. In Jul–Sep 2022 and Jul–Aug 2023, I was a visiting researcher at EnICS labs. In Jan–Feb 2024, I was a visiting researcher at the Department of Information Engineering, University of Pisa, Italy.
I am an IEEE Senior Member. I have authored/coauthored more than 65 scientific papers in international peer-reviewed journals and conferences, and have participated in several IC tapeouts. I have received several awards, research grants, and funding (as Principal Investigator). I have been part of several IEEE conference committees and journal boards, and I am an active reviewer for journals (IEEE, Elsevier, Frontiers, Wiley) and conferences.
Research Areas
Memory-Centric Accelerators
Domain-specific hardware that computes inside or beside the memory array, removing the data-movement bottleneck in machine learning, graph processing and similarity search.
MRAM & Spintronics
STT-MRAM built on single- and double-barrier magnetic tunnel junctions for non-volatile, energy-efficient embedded memory — including cryogenic operation.
Content-Addressable Memory
Approximate-match CAM architectures with tunable Hamming distance, applied to DNA classification and on-chip genome analysis.
Low-Power VLSI Design
Transistor-level design and silicon validation of SRAM, sensing circuits and analog blocks in advanced CMOS, FinFET and SOI technologies.
Latest News
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21 Aug, 2025
Received the 2025 USFQ Post-Graduate Alumni Award!
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08 May, 2025
2025 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award! (link)
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21 April, 2025
Serving as Technical Program Chair at the 1st IEEE International Conference on Application of Information Technologies in Engineering, Management and Science (ICAI-TEMS)
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17 October, 2024
Included in the World's Top 2% Scientists according to the prestigious Stanford/Elsevier's list.
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09 July, 2024
Obtained the National Scientific Habilitation (ASN) for Associate Professor of Electronics (Sector 09/E3) in Italian Universities.
Upcoming Events
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November 11-14, 2025
1st IEEE International Conference on Application of Information Technologies in Engineering, Management and Science (ICAI-TEMS)
Funding & Sponsors
