Talks
See where these talks took me on the travel map.
Personal Talks in Conferences
- STT-MRAM-based Content-Addressable Memory for In-Memory and Neuromorphic Computing
To be Presented at: IEEE Trends in Magnetism Conference (TMAG), Milan, Italy, 07-11 Sep. (2026) - PatBiNN: A 65nm Processing-in-CAM Based BNN Implementation for Pathogen Genome Classification
Y. Harary, A. Sharoni, , L. Yavits
2026 Design, Automation & Test in Europe Conference (DATE), Verona, Italy, 20-22 April (2026) - IMAP: In-MRAM Associative Processor with reliable bit-serial massively-parallel arithmetic operations (INVITED)
, C. Mosquera, M. Lanuzza
Spintronics and Nanomagnetism Conference - SPIE Photonics Europe, Strasbourg, France, 12-16 April (2026) - Hardware Accelerators For A Sustainable AI Future
IEEE International Conference on Application of Information Technologies in Engineering, Management and Science (ICAI-TEMS), Rende, Italy, 11-14 Nov. (2025) - ISPA: In-Situ Processing within Associative Processor for Energy-Efficient Computations
IEEE Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), Dresden, Germany, 08-10 Oct. (2025) - Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations
A. Bedoya, B. Zambrano, R. Taco, LM. Prócel, M. Lanuzza,
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025) - Towards Low-Power High-Performance Content-Addressable Memory: a Robust Precharge-Free Approach
R. Taco, , A. Teman, L. Yavits, M. Lanuzza
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025) - Low Matchline Voltage Swing Content-Addressable Memory Cell
C. Mosquera, R. Taco, B. Zambrano, LM. Prócel, , M. Lanuzza
IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025) - STT-MRAM technology for energy-efficient 2-D and 3-D associative in-data processing architectures
, M. Lanuzza
IEEE Conference on Advances in Magnetics (AIM), Bressanone, Italy, 09-13 Feb. (2025) - Fully CMOS Ising machine for combinatorial optimization and probabilistic sampling problems
, M. Lanuzza
The International Workshop on Ising Machines (IISM), Messina, Italy, 16-18 April (2024) - A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory
, R. Golman, M. Lanuzza, A. Teman, L. Yavits
IEEE International Symposium on Integrated Circuits and Systems (ISICAS), Jeju, South Korea, 24-25 Oct. (2023) - MRAM Based Associative Memory For In-Memory Computing
, M. Lanuzza
IEEE Trends in Magnetism Conference (TMAG), Rome, Italy, 04-08 Sep. (2023) - STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications
, L. Yavits, A. Teman, M. Lanuzza
IEEE Latin American Symposium on Circuits and Systems (LASCAS), Quito, Ecuador, 28 Feb.-02 Mar. (2023) - Content-Addressable Memory for Approximate Matching Applications in Genome Analysis
, M. Lanuzza
53rd Annual Meeting of the Associazione Società Italiana di Elettronica (SIE), Pizzo (VV), Italy, 09 Sep. (2022) - A RISC-V-based Research Platform for Rapid Design Cycle
, R. Golman, O. Harel, T. Noy, Y. Kra, A. Pollock, S. Yuzhaninov, Y. Shoshan, Y. Rudin, Y. Weitzman, et al.
IEEE International Symposium on Circuits and Systems (ISCAS), Austin Texas, USA, 28 May-01 Jun. (2022) - Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories
, R. Taco, L.M. Prócel, L. Trojman, M. Lanuzza
IEEE Latin American Symposium on Circuits and Systems (LASCAS), Puerto Varas, Chile, 01-04 Mar. (2022) - Dual-Barrier MTJ Based Cryogenic STT-MRAMs
, M. Carpentieri, M. Lanuzza
IEEE Trends in Magnetism Conference (TMAG), Cefalù, Italy, 06-10 Sep. (2021) - Relaxing Non-Volatility for Energy-Efficient DMTJ Based Cryogenic STT-MRAM
, R. De Rose, F. Crupi, L. Trojman, A. Teman, M. Lanuzza
22nd Conference on Insulating Films on Semiconductors (INFOS), Rende, Italy, 28 Jun.–08 Jul. (2021) - Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory
, R. De Rose, F. Crupi, M. Lanuzza
IEEE International Conference on Electronics Circuits and Systems (ICECS), Genova, Italy, 27-29 Nov. (2019) - Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
, R. De Rose, F. Crupi, L. Trojman, G. Finocchio, M. Carpentieri, M. Lanuzza
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15-18 Jul. (2019)
Invited Talks & Seminars
- (2026) "IMAP -- In-MRAM Associative Processor with reliable bit-serial massively-parallel arithmetic operations", Spintronics and Nanomagnetism Conference - SPIE Photonics Europe, Strasbourg, France, 12-16 April
- (2025) "In-Memory Processing-Based Hardware Accelerators For Transformer Architectures", International Online Workshop on In-Memory and In-Storage Processing, Korean Institute of Information Scientists and Engineers (KIISE) and the Computer Society of Iran (CSI), 25-26 Sept.
- (2023) "Spintronic Technology For Energy-Efficient hybrid CMOS/MTJ Memory Applications", University of Calabria, Rende, Italy, 14-15 Jun.
- (2023) "Hybrid CMOS/MTJ Circuit Design", Politecnico di Bari, Bari, Italy, 15-16 May
- (2022) "Spin-Transfer Torque Magnetic RAM For Embedded Memory Applications", IEEE CAS Ecuador Chapter, Quito, Ecuador, 10 Jun.
- (2021) "STT-MRAMs for Cryogenic Non-Volatile Cache Applications", Microelectronic Week, IEEE EDS-CAS Ecuador Joint Chapter, Quito, Ecuador, 10 Oct.