PIMAT publications
Publications
- Total Number of peer-reviewed publications: 17
- Journals: 7
- Conferences: 10
- A complete list of the PI’s publications: link
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SRAM-Based Processing-in-Memory Cell Enabling Binary Neural Networks Through XNOR Multiplication and Charge-Domain Accumulation to be presented at IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2026...Loading… -
Reliability and Assessment of an MRAM-based Non-Volatile Precharge-Free Ternary CAM for Real-Time Edge Inference to be presented at IEEE Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2026Non-volatile content-addressable memories (NVCAMs) based on magnetic tunnel junctions (MTJs) are emerging as a compelling processing-using-memory (PuM) scheme for energy-efficient, massively-parallel pattern matching in AI inference and edge-computing workloads. This paper presents a comprehensive reliability and application-level study of a hybrid MTJ-CMOS NV precharge-free ternary CAM (NV-PTCAM) designed in a commercial 65 nm CMOS process. At the circuit level, we evaluate the impact of the number of ternary ‘don’tcare’ (X) states stored within the NV-TPCAM, and the impact of row segmentation. NV-PTCAM achieves a search delay below 0.25 ns, a search energy consumption of 1.82 fJ/cell, and a search error rate of about 0.02%, outperforming conventional NV-NOR and NV-NAND counterparts by up to 82% in search energy and up to 11.5× in search delay, on average. We apply an endurance model to the NV-PTCAM search workload and demonstrate that the number of cycles to failure exceeds 1013 for pulse amplitudes as high as 0.656V and pulse widths in the range 100- 500 ps, establishing the practical reliability of the NV-PTCAM for explainable artificial intelligence (xAI) models useful in wearable or edge devices. At the application level, we demonstrate the NV-PTCAM as the PuM inference engine of a real-time photoplethysmography (PPG)-based tachycardia classifier. The NV-PTCAM-based Random-Forest-based PuM system achieves a mean accuracy of 94.8% and an F1-score of 86.7% on the BIDMC clinical dataset, while the low SER of the NV-PTCAM has a negligible impact on classification performance.Loading… -
AM5: Bulk Logic-in-Memory Using MRAM NAND Crossbar IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2026Application domains, such as machine learning and big data analytics, impose significant computational challenges to contemporary Von Neumann architectures. To address this issue, logic-in-memory (LiM) has been raised as a promising alternative that targets computing within memory arrays, aimed at alleviating the memory wall, optimizing data transfer, and enabling massive parallelism. Spin-transfer torque magnetic tunnel junction (STT-MTJ) based memory is an emerging memory technology that enables efficient processing using memory. This paper proposes AM5, a novel LiM architecture leveraging MRAM NAND crossbar technology to support in-memory arithmetic operations efficiently. The proposed LiM scheme is designed using a commercial 28nm process node and a Verilog-A-based double-barrier MTJ compact model. Evaluation results show that AM5 consumes about 98 fJ/40.7 fJ/DMTJ per evaluation/write cycle (4.2-4.4 ns/1.9 ns). Additionally, the proposed architecture proposes an in-situ error correction mechanism to mitigate variability, yielding reliable arithmetic operations. These findings show better energy (∼ 6× lower, on average) and competitive latency (∼ 1.3× faster, on average) figures of AM5 compared to other LiM designs based on MTJ-based technology. When used as a LiM unit to perform inference in adder attention Vision Transformer networks, AM5 consumes about one-tenth of the energy required by a processor-centric unit.Loading… -
IMAP: In-MRAM Associative Processor with reliable bit-serial massively-parallel arithmetic operations Spintronics and Nanomagnetism Conference - SPIE Photonics Europe (INVITED), 2026The ever-growing demand for data-intensive applications has driven the adoption of in-memory computing (IMC) as a promising paradigm to overcome the von Neumann bottleneck of conventional computing architectures. Among the emerging memory technologies explored for IMC-based architectures, magnetic random-access memory (MRAM) stands out due to its non-volatility, high endurance, and compatibility with standard CMOS fabrication process. This work presents IMAP, an in-MRAM associative processor based on perpendicular anisotropy double-barrier magnetic tunnel junctions (DMTJs) with two reference layers. IMAP presents processing units built with NAND-type content-addressable memory (CAM) architecture, allowing bit-serial massivelyparallel arithmetic operations. Reliable and energy-efficient in-memory computing operations are achieved by properly carrying out a data allocation technique to mitigate variability-induced errors arising from the limited ratio between high-resistance and low-resistance states. IMAP is designed using a commercial 28 nm process and a Verilog-A-based compact DMTJ model calibrated with experimental physical parameters. Circuit-level Monte Carlo simulations demonstrate correct operation under worst-case conditions and show that the proposed data allocation increases the probability of correct 8-bit full-adder operations for the most significant bits from about 63% to approximately 95%. At the application level, IMAP is evaluated as an accumulator in a fixed-point twodimensional convolution workload, where the proposed approach improves the output peak signal-to-noise ratio from 6.21 dB to 24.26 dB. The obtained results indicate that IMAP can efficiently accelerate arithmetic kernels associated with contemporary data-centric applications, thereby suggesting MRAM-based associative processing as a potential IMC architecture for future memory-centric computing systems.Loading… -
SPARCAM: Sparse Matrix Multiplication Accelerator Using Multi-Port Dynamic CAM Journal of Systems Architecture (JSA), 2026Sparse General matrix multiplication (SpGEMM) is a fundamental kernel in many scientific and engineering fields, including Generative AI. However, its intrinsic computation complexity presents substantial challenges, making efficient hardware implementation particularly difficult. This paper proposes SPARCAM, a novel SpGEMM accelerator, developed and optimized for very energy-efficient Generative AI edge applications. SPARCAM is designed using low-power dense Gain Cell embedded DRAM (GC-eDRAM) technology, a processing near memory paradigm, and a modified outer product matrix multiplication algorithm. Despite its quite limited peak theoretical performance, SPARCAM achieves very high energy efficiency due to its low-power architecture and almost 100% utilization of its computing resources. Designed in a commercial 28nm FDSOI technology, SPARCAM achieves 13.9× speedup over a high-performance embedded CPU when processing large-scale sparse matrices. When multiplying limited-size sparse matrices, SPARCAM obtains 193× speedup over high-performance GPU. SPARCAM reaches about 4.3 orders-of-magnitude, on average, higher energy benefits, and 1892×, 181×, 2×, and 3471×, higher energy efficiency (over CPU) compared with state-of-the-art SpGEMM accelerators SpArch, OuterSPACE, MatRaptor, and high-performance GPU, respectively.Loading… -
CADM: Content Addressable Commodity Off-the-Shelf DRAM-Based Genome Classifier Journal of Systems Architecture (JSA), 2026Processing using memory (PuM) leverages analog properties of memory infrastructure to implement logic and arithmetic operations. Commodity Off-The-Shelf (COTS) DRAM is particularly attractive for PuM because it requires no device modification, thereby preserving the ubiquity, availability, and cost advantages of modern DRAM while enabling massive column-level parallelism. We propose CADM (Content-Addressable DRAM), that enables exact and approximate (similarity) search in- and usingunmodified COTS DRAM. CADM targets genome classification, which is one of the most important applications in bioinformatics. Specifically, rapid and accurate detection of bacterial pathogens is critical for effective clinical decision-making, particularly in life-threatening conditions such as sepsis, where early identification of the causative agent significantly improves patient outcomes. We implement CADM in commercial DDR4 and show that it can achieve up to 185× higher throughput and 73× energy savings compared to CPU-run state-of-the-art classifier Kraken2. Using approximate search, CADM can achieve 9× higher F1 score when matching relatively short (<32 DNA bases) ambiguous and erroneous k-mers.Loading… -
Integrated BSI Bacteria Identifier-On-Chip Using Approximate k-mer Matching Scientific Reports, 2026Acute graft-versus-host (GVHD) is a deadly disease that can be treated through fecal microbiota transplantation. However, such treatment is often followed by life-threatening bloodstream infections (BSI). Rapid detection of BSI-causing bacteria is critical in preventing BSI-related deaths. PC-CAM is a pathogen identification system-on-chip designed to assist in avoiding BSI by real-time detection of pathogen bacterial genomes using k-mer matching. The core of PC-CAM is an Approximate search-capable (Hamming distance tolerant) Content Addressable Memory (ACAM). PC-CAM was designed and manufactured in a commercial 65nm process. We use PC-CAM for real-time detection of bacteria in blood and stool samples of GVHD patients and evaluate PC-CAM bacteria identification efficiency, performance, silicon area, and power consumption based on silicon measurements. PC-CAM is capable of classifying 960K short DNA reads/sec within a silicon area of 2.38mm2 consuming about 1.27mW. We envision PCCAM as a platform deployed at points of care to provide real-time, accurate, privacy-preserving, easy-to-operate, and energy-efficient pathogen classification.Loading… -
GenMClass: Design and comparative analysis of genome classifier-on-chip platform Journal of Systems Architecture (JSA), 2026We propose GenMClass, a genome classification system-on-chip (SoC) implementing two different classification approaches and comprising two separate classification engines: a DNN accelerator GenDNN, that classifies DNA reads converted to images using a classification neural network, and a similarity search-capable Error Tolerant Content Addressable Memory ETCAM, that classifies genomes by k-mer matching. Classification operations are controlled by an embedded RISCV processor. GenMClass classification platform was designed and manufactured in a commercial 65nm process. We conduct a comparative analysis of ETCAM and GenDNN classification efficiency as well as their performance, silicon area and power consumption using silicon measurements. The size of GenMClass SoC is 3.4mm2 and its total power consumption (assuming both GenDNN and ETCAM perform classification at the same time) is 144mW. This allows using GenMClass as a portable classifier for pathogen surveillance during pandemics, food safety and environmental monitoring, agriculture pathogen and antimicrobial resistance control, in the field or at points of care.Loading… -
PatBiNN: A 65nm Processing-in-CAM Based BNN Implementation for Pathogen Genome Classification 2026 Design, Automation & Test in Europe Conference (DATE), 2026Binary Neural Networks (BNNs) are a cost-effective and highly efficient alternative to traditional neural networks. Genome classification is a frequent component of genome analysis pipelines, with a variety of applications spanning pandemic preparedness, AMR resistance control, drinking water and food safety. PatBiNN is a BNN based pathogen genome classifier optimized for edge and field use. It employs a binary multilayer perceptron (MLP) implemented using in-Hamming distance tol- erant (similarity search) content addressable memory processing. PatBiNN was designed and manufactured in a commercial 65nm process. It achieves F1 score of 88%, ROC AUC of 0.986, throughput of 0.8M inferences/s, power consumption of 4.8 mW and energy efficiency of 237TOPs/s/W with silicon area of 0.87mm2.Loading… -
NV-PCAM: Non-Volatile Precharge-Free Content-Addressable Memory IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2025Content-addressable memories (CAMs) are a class of associative memories known for their capability to perform massively parallel comparisons between an input query pattern and the entire memory content. In the past decade, the increasing demand for high-performance and energy-efficient computing systems has generated significant interest in non-volatile CAMs (NV-CAMs) based on emerging non-volatile memory devices. In this work, we propose a novel non-volatile, precharge-free CAM (NV-PCAM) scheme based on double-barrier magnetic tunnel junctions (DMTJs). When compared to its counterparts, NV-PCAM presents competitive figures of merit in terms of area, speed, and energy efficiency, while also ensuring low search error rates. We also provide a complete class of voltage-divider-based NV-CAM cells for benchmark comparison. All schemes are designed and laid out using a 65 nm process and evaluated under Monte Carlo and process-voltage-temperature (PVT) simulations. Through Monte Carlo simulations, the proposed NV-PCAM demonstrates up to 81% and 85% lower search energy than NV-NOR and NV-NAND, respectively, as well as a 61% and 16% improvement in terms of search delay with a compact cell area footprint.Loading… -
Hardware Accelerators For A Sustainable AI Future IEEE International Conference on Application of Information Technologies in Engineering, Management and Science (ICAI-TEMS), 2025The exponential growth of the use of artificial intelligence (AI) in all sectors of our society is driving unprecedented energy consumption and carbon dioxide emissions, threatening both the environment and the scalability of future AI technologies. This growing concern is especially pronounced in the context of transformer-based generative AI models, whose computational and energy demands continue to escalate rapidly. Addressing this challenge necessitates a shift from contemporary computing through the integration of novel computing paradigms and specialized hardware accelerators that significantly improve performance-per-watt efficiency. This work discusses the power-intensive nature of generative AI technologies, reviews current trends in AI hardware, and provides a forward-looking perspective on hardware accelerators, with a particular emphasis on memory-centric computing, specifically optimized for AI applications. By reviewing algorithmic and architectural advances, this work shows the central role of hardware innovation in enabling energy-efficient and scalable generative AI systems.Loading… -
A Low-Power 4-bit Tracking-Type Analog-to-Digital Converter in SKY130 Process IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2025This paper presents the design and full-custom layout implementation of a 4-bit Tracking-Type Analog-to-Digital Converter (TT-ADC) using the SKY130 130 nm CMOS process. The proposed architecture mainly integrates a rail-to-rail analog comparator and a multiplexed resistor-string Digital-to-Analog Converter (DAC), combined with a synchronous controller and an output register. Unlike traditional tracking ADCs, this work introduces a fully integrated mixed-signal design optimized for both bandwidth and power efficiency, and evaluated under process-temperature-voltage variations accounting for layout parasitics. Simulations show that the proposed TT-ADC presents a bandwidth of 150 MHz while consuming only 505μ W of power. Compared to prior 4-bit implementations, the proposed design achieves over 2× improvement in bandwidth and an 87% reduction in power consumption. The area footprint is about 54.9μm×29.3μm, making it highly suitable for energyconstrained, high-speed embedded applications.Loading… -
PiC-BNN: A 128-kbit 65nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator IEEE Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2025Binary Neural Networks (BNNs), where weights and activations are constrained to binary values (+1, -1), are a highly efficient alternative to traditional neural networks. Unfortunately, typical BNNs, while binarizing linear layers (matrix-vector multiplication), still implement other network layers (batch normalization, softmax, output layer, and sometimes the input layer of a convolutional neural network) in full precision. This limits the area and energy benefits and requires architectural support for full precision operations. We propose PiC-BNN, a true end-to-end binary in-approximate search (Hamming distance tolerant) Content Addressable Memory based BNN accelerator. PiC-BNN is designed and manufactured in a commercial 65nm process. PiC-BNN uses Hamming distance tolerance to apply the law of large numbers to enable accurate classification without implementing full precision operations. PiC-BNN achieves baseline software accuracy (95.2%) on the MNIST dataset and 93.5% on the Hand Gesture (HG) dataset, a throughput of 560K inferences/s, and presents a power efficiency of 703M inferences/s/W when implementing a binary MLP model for MNIST/HG dataset classification.Loading… -
An Accurate And Low Complexity Offset Calibration Methodology for Dynamic Comparators Journal of Low Power Electronics and Applications (JLPEA), 2025Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit, and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a 1-sigma offset of 0.223mV, while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration.Loading… -
Towards Low-Power High-Performance Content-Addressable Memory: a Robust Precharge-Free Approach IEEE International Symposium on Circuits and Systems (ISCAS), 2025Low-power high-performance content-addressable memories (CAMs) are important components in modern computing systems. In this work, we present a robust CAM that overcomes the power and performance limitations of conventional precharge-based CAMs. The proposed static transmission gatebased (STAT-TG) CAM design achieves low-power operation comparable to NAND CAMs while maintaining search speeds rivaling those of NOR CAMs. The STAT-TG CAM was designed using a 65nm CMOS technology and comprehensively evaluated under extensive Monte Carlo simulations. Compared to conventional CAMs, the STAT-TG CAM is 14% faster than NAND CAM, while consuming only 25% of the energy per operation relative to NOR CAM. This makes STAT-TG CAM a promising solution for high-performance yet energy-efficient applications.Loading… -
Low Matchline Voltage Swing Content-Addressable Memory Cell IEEE International Symposium on Circuits and Systems (ISCAS), 2025Content-addressable memory (CAM) is a specialized memory architecture designed for fast data searches, allowing a one-clock-cycle comparison between the search input and the entire memory content. In this work, a low matchline voltage swing CAM is proposed to reduce the search power consumption while maintaining high-speed search operations. Low voltage swing in the matchline is enabled by introducing extra circuitry in the conventional CAM cell. By means of comprehensive Monte Carlo and post-layout simulations using a commercial 65 nm node, we show that the proposed CAM cell design allows for robustness against process, voltage, and temperature variations without the need for dedicated matchline sense schemes. Compared to conventional precharge high NOR-type CAM, the proposed design achieves 42% higher speed and 29.1% less energy consumption. Post-layout results demonstrate that the proposed CAM operates reliably at 0.6V, maintaining performant and reliable search operations across a wide temperature range.Loading… -
Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations IEEE International Symposium on Circuits and Systems (ISCAS), 2025This work presents a non-volatile contentaddressable memory (NV-CAM) based on double-barrier magnetic tunnel junction technology (DMTJ). Unlike state-ofthe- art NV-CAM designs that present low-performance updates, our NV-CAM allows energy-efficient, high-performance search and update operations. This makes it well-suited for applications requiring a high frequency of searches/updates, such as associative processors. The NV-CAM hybrid CMOS/DMTJ was designed using a commercial 65nm CMOS technology and a Verilog-A-based DMTJ compact model. The NV-CAM evaluation was carried out by employing Monte Carlo simulations while accounting for process variations. Simulation results show that our NV-CAM presents competitive figures of merit compared to state-of-the-art design. Our NV-CAM presents energy-efficient operations and reduces the update and search delay by about 71% and 75%, respectively, compared to other NV-CAMs.Loading…
Deliverables & Milestones
| Item | WP | Description | Status | File |
|---|---|---|---|---|
| D3.1 | WP3 | Benchmarking and Assessment | ✔ Delivered/ready at M16 | -- |
| D4.5 | WP4 | Dissemination, communication, and exploitation plan | ✔ Delivered/ready at M16 | -- |
| MS4 | WP4 | Dissemination, communication, and exploitation plan | ✔ Milestone Achieved at M1 | link |
| D4.1 | WP4 | Dissemination, communication, and exploitation plan | ✔ Delivered/ready at M1 | -- |
| D5.1 | WP5 | Data management plan | ✔ Delivered/ready at M1 | -- |
| D5.2 | WP5 | Risk management plan | ✔ Delivered/ready at M2 | -- |
| D5.3 | WP5 | Partners Agreement | ✔ Delivered/ready at M3 | -- |
| D1.1 | WP1 | Desk research: SOTA analysis | ✔ Delivered/ready at M3 | -- |
| D1.2 | WP1 | Algorithm-hardware co-design and optimization | ✔ Delivered/ready at M7 | -- |
| D4.2 | WP4 | Hardware for Transformer Networks | ✔ Delivered/ready at M11 | -- |
| D2.1 | WP2 | IC design report | ✔ Delivered/ready at M13 | -- |
| MS1 | WP1 | HW-oriented algorithm defined | ✔ Delivered/ready at M14 | -- |
Tapeouts
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Other Resources
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