The design of hardware accelerators that use memory technologies and computing paradigms to address the limitations of conventional processor-centric architectures in data-intensive workloads. The memory technologies include static RAM (SRAM), dynamic RAM (DRAM), and emerging non-volatile memories (e.g., MRAM, RRAM) with a particular focus on enhancing energy efficiency, computational throughput, and memory access locality. The computational paradigms include in-memory computing and near-memory computing, where data-intensive operations are performed within or close to the memory arrays to alleviate the data movement bottleneck. These paradigms are especially relevant for workloads in machine learning, graph processing, similarity search, and real-time analytics.
Representative case studies include the development of application-specific accelerators that leverage content-addressable computation for approximate search, sparse matrix-vector multiplication, and machine learning networks (e.g., binarized neural networks). The designs are validated through a hardware/software co-design methodology, incorporating low-level circuit simulations, architectural modeling, and high-level application integration.
Non-volatile spintronic memories represent a promising knob to deal with the increased leakage power resulting from the scaling down of CMOS technology towards the end of Moore’s law. In particular, spin-transfer torque magnetic random access memories (STT-MRAMs) based on perpendicular magnetic tunnel junctions (pMTJs) are already on the market with potential improvements targeting low-power and high-speed operation, high density, high endurance, long data retention time, low fabrication cost, and easy integration with CMOS processes. Thanks to the above properties, STT-MRAMs are actually considered premier candidates for replacing conventional semiconductor-based cache memories at more scaled technology nodes. However, one of the main challenges for a wider spread of STT-MRAMs is the reduction of their writing currents for both energy and area savings.
My research activity is focused on, but not limited to, non-volatile cache memories implemented by STT-MRAMs.
The main research topics cover (not limited to):