Table of Contents

Personal Talks in Conferences

  1. Non-Volatile Content-Addressable Memory for Energy-Efficient & High-Performance Search and Update Operations
    A. Bedoya, B. Zambrano, R. Taco, LM. Prócel, M. Lanuzza, E. Garzón, IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025)
  2. Towards Low-Power High-Performance Content-Addressable Memory: a Robust Precharge-Free Approach
    R. Taco, E. Garzón, A. Teman, L. Yavits, M. Lanuzza, IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025)
  3. Low Matchline Voltage Swing Content-Addressable Memory Cell
    C. Mosquera, R. Taco, B. Zambrano, LM. Prócel, E. Garzón, M. Lanuzza, IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 25-28 May. (2025)
  4. STT-MRAM technology for energy-efficient 2-D and 3-D associative in-data processing architectures
    E. Garzón, M. Lanuzza, IEEE Conference on Advances in Magnetics (AIM), Bressanone, Italy, 09-13 Feb. (2025)
  5. Fully CMOS Ising machine for combinatorial optimization and probabilistic sampling problems
    E. Garzón, M. Lanuzza, The International Workshop on Ising Machines (IISM), Messina, Italy, 16-18 April (2024)
  6. A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory
    E. Garzón, R. Golman, M. Lanuzza, A. Teman, L. Yavits, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), Jeju, South Korea, 24-25 Oct. (2023)
  7. MRAM Based Associative Memory For In-Memory Computing
    E. Garzón, M. Lanuzza, IEEE Trends in Magnetism Conference (TMAG), Rome, Italy, 04-08 Sep. (2023)
  8. STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications
    E. Garzón, L. Yavits, A. Teman, M. Lanuzza, IEEE Latin American Symposium on Circuits and Systems (LASCAS), Quito, Ecuador, 28 Feb.-02 Mar. (2023)
  9. Content-Addressable Memory for Approximate Matching Applications in Genome Analysis
    E. Garzón, M. Lanuzza, 53rd Annual Meeting of the Associazione Società Italiana di Elettronica (SIE), Pizzo (VV), Italy, 09 Sep. (2022)
  10. A RISC-V-based Research Platform for Rapid Design Cycle
    E. Garzón, R. Golman, O. Harel, T. Noy, Y. Kra, A. Pollock, S. Yuzhaninov, Y. Shoshan, Y. Rudin, Y. Weitzman, et al., IEEE International Symposium on Circuits and Systems (ISCAS), Austin Texas, USA, 28 May-01 Jun. (2022)
  11. Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories
    E. Garzón, R. Taco, L.M. Prócel, L. Trojman, M. Lanuzza, IEEE Latin American Symposium on Circuits and Systems (LASCAS), Puerto Varas, Chile, 01-04 Mar. (2022)
  12. Dual-Barrier MTJ Based Cryogenic STT-MRAMs
    E. Garzón, M. Carpentieri, M. Lanuzza, IEEE Trends in Magnetism Conference (TMAG), Cefalù, Italy, 06-10 Sep. (2021)
  13. Relaxing Non-Volatility for Energy-Efficient DMTJ Based Cryogenic STT-MRAM
    E. Garzón, R. De Rose, F. Crupi, L. Trojman, A. Teman, M. Lanuzza, 22nd Conference on Insulating Films on Semiconductors (INFOS), Rende, Italy, 28 Jun.–08 Jul. (2021)
  14. Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory
    E. Garzón, R. De Rose, F. Crupi, M. Lanuzza, IEEE International Conference on Electronics Circuits and Systems (ICECS), Genova, Italy, 27-29 Nov. (2019)
  15. Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
    E. Garzón, R. De Rose, F. Crupi, L. Trojman, G. Finocchio, M. Carpentieri, M. Lanuzza, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15-18 Jul. (2019)

Invited Talks/Seminars

  1. (2025) "In-Memory Processing-Based Hardware Accelerators For Transformer Architectures", International Online Workshop on In-Memory and In-Storage Processing, Korean Institute of Information Scientists and Engineers (KIISE) and the Computer Society of Iran (CSI), 25-26 Sept.
  2. (2023) "Spintronic Technology For Energy-Efficient hybrid CMOS/MTJ Memory Applications", University of Calabria, Rende, Italy, 14-15 Jun.
  3. (2023) "Hybrid CMOS/MTJ Circuit Design", Politecnico di Bari, Bari, Italy, 15-16 May
  4. (2022) "Spin-Transfer Torque Magnetic RAM For Embedded Memory Applications", IEEE CAS Ecuador Chapter, Quito, Ecuador, 10 Jun.
  5. (2021) "STT-MRAMs for Cryogenic Non-Volatile Cache Applications", Microelectronic Week, IEEE EDS-CAS Ecuador Joint Chapter, Quito, Ecuador, 10 Oct.